1. Field of the Invention
The present invention relates to a method for manufacturing an embedded dynamic random access memory (DRAM) self-aligned with borderless contacts (SAC) and more particularly to a method in combining a logic region with borderless contact windows and a dynamic random access memory (DRAM).
2. Description of the Prior Art
In recent years, due to the use of electronic components in a great quantity the need of semiconductor devices is increasing rapidly, and in particular due to the widespread of computerization, this need is even more accelerated. Hundreds and thousands of transistors are needed in creating a highly complex integrated circuit. In order to improve the manufacturing of electronic devices within an integrated circuit of a single semiconductor chip, a highly integrated but diminished layout is required to improve the quality of semiconductor devices.
Knowing that the requirement for integration is greater, combining a logic region with a DRAM is widespread when applied on chips. Bit-line contact windows and node contact windows in DRAM have normally been designed as self-aligned contacts (SACs) so to reduce the occupied chip area.
Dynamic Random Access Memory (DRAM) is one of the main volatile memories, and the so-called xe2x80x9csingle transistor DRAM cellxe2x80x9d is made up of a metal oxide semiconductor (MOS) transistor and a capacitor.
In accompanying with the requirement of high integration, the size of MOS and the line width of metallic lines have become smaller and smaller. When making a contact between a metallic line and a source or drain region of a MOS, contact between part of the metallic line and shallow trench isolation (STI) might occur. This is a problem because the size of the source/drain region is smaller than the metallic line or because miss-alignment between the metallic line and the source/drain region. Once the miss-alignment occurs, an insulation of the shallow trench isolation should not be affected. In ensuring that and without any reduction in device integration, a manufacturing method for borderless contact is generated.
Nevertheless, during the combining process between a logic region with borderless contacts and a DRAM, a silicon nitride layer that is used as an etching stop layer at the logic region is deposited after the formation of salicide of the drain/source region. Therefore, difficulties might occur during an etching process of DRAM self-aligned contacts.
In accordance with the present invention, problems induced during the combining process between a logic region and a memory region exists. The main objective of the present invention is to overcome all the drawbacks caused during the self-aligned contact etching process by removing an etching stop silicon nitride layer for borderless contacts within the memory region. Eventually, moving toward a successful combination between the logic region and the memory region.
Another objective of the present invention is to provide a fabricating method, that by is capable of reducing a short circuit phenomena generated during an etching process in between a bit-line and a polysilicon gate within the memory region.
A method for manufacturing an embedded DRAM with self-aligned borderless contacts is provided. The method comprises providing a substrate having a first device region and a second device region. The first device region comprises a first transistor and the second device region has a second transistor. A silicide block layer is formed over the second device region. An etching stop layer covers all device regions. A mask layer covers the first device region. Then the etching stop layer not covered by the mask layer is removed. A first dielectric material layer is formed on all the device regions and therein a first contact window is on the second device region. A second dielectric material layer is formed next and therein a second contact window is on the second device region. A third dielectric material layer is formed and therein at least a third contact window is coupled to the first transistor of the first device region. A metallic node is formed on the third contact window.